library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clock is
    Port (clk : in  STD_LOGIC;
		rst : in  STD_LOGIC;
		K1 : in  STD_LOGIC;
		K2 : in  STD_LOGIC;
		K3 : in  STD_LOGIC;
		seg1 : out  STD_LOGIC_VECTOR (6 downto 0);
		seg2 : out  STD_LOGIC_VECTOR (6 downto 0);
		seg3 : out  STD_LOGIC_VECTOR (15 downto 0));
end clock;

architecture Behavioral of clock is
	signal clk_out : std_logic:='0';
	signal cnt: std_logic_vector(25 downto 0):="00000000000000000000000000";
	signal cnt_H:std_logic_vector(3 downto 0):="0000";	
	signal cnt_L:std_logic_vector(3 downto 0):="0000";
begin

process(clk)
begin
	if(clk'event and clk='1')then
		cnt<=cnt+'1';
		if(cnt ="00000000000000000000000000") then
			 clk_out<='0';
		end if;
		if(cnt ="01011011100011011000000000") then
			 cnt<="00000000000000000000000000";
			 clk_out<='1';
		end if;
	end if;
end process;

process(clk_out,rst,K1)
	variable tmp_H,tmp_L:std_logic_vector(3 downto 0):="0000";
begin
	if(rst ='0')then
		tmp_H :="0000";
		tmp_L :="0000";
		elsif(K1 ='0')then
		tmp_H :="0000";
		tmp_L :="0000";
		elsif(K2 ='0')then
		tmp_H :="0100";
		tmp_L :="0000";
		elsif(K3 ='0')then
		tmp_H :="1000";
		tmp_L :="0000";
	else
		if(clk_out'event and clk_out='1')then
			tmp_L :=cnt_L+'1';
			if(tmp_L>"1001") then
				tmp_L :="0000";
				tmp_H :=cnt_H+'1';
				if(tmp_H>"1001") then
					 tmp_H :="0000";
				end if;
			end if;
		end if;
	end if;
	cnt_L<=tmp_L;
	cnt_H<=tmp_H;

end process;

process(cnt_H)
begin
	case cnt_H is
		when "0000"=>seg3<=not "0000000000000000";
		when "0001"=>seg3<=not "0000000000001111";
		when "0010"=>seg3<=not "0000000011111111";
		when "0011"=>seg3<=not "1111111111111111";
		when "0100"=>seg3<=not "0000000000000000";
		when "0101"=>seg3<=not "0000000000001111";
		when "0110"=>seg3<=not "0000000011111111";
		when "0111"=>seg3<=not "1111111111111111";
		when "1000"=>seg3<=not "0000000000000000";
		when "1001"=>seg3<=not "0000000000001111";
		when others=>seg3<=not "0000000011111111";
	end case;
end process;
process(cnt_H)
begin
	if( cnt_H<"0100") then
       seg1<= "0000001";
		 seg2<= "0000001";
		 elsif(cnt_H>"0011" and cnt_H<"1000") then
		 seg1<= "1000000";
		 seg2<= "1000000";
		 elsif(cnt_H>"0111" and cnt_H<"1011") then
		 seg1<= "0001000";
		 seg2<= "0001000";
		-- end if;
	--	end if;  
	end if;
end process;
end Behavioral;

